1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including transistor elements comprising gate structures formed on the basis of a high-k gate dielectric material and a metal-containing electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to the substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice in the near future for circuits designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of the gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously reduced to improve switching speed and drive current capability. Since the transistor performance in terms of switching speed and drive current is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be ensured. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage, and thus reduced threshold voltage, may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold of the completed transistor structures. For instance, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. Moreover, a shift of the work function may be observed when forming appropriate work function metals in an early manufacturing stage, which is believed to be caused by a moderately high oxygen affinity of the metal species, in particular during high temperature processes which may typically be required for completing the transistor structures, for instance, for forming drain and source regions and the like.
For this reason, in some approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal, possibly in combination with a high-k dielectric material, and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure. In a corresponding replacement gate approach, the high-k dielectric material, if provided in this stage, may be covered by an appropriate metal-containing material, such as titanium nitride and the like, followed by a standard polysilicon or amorphous silicon material, which may then be patterned on the basis of well-established advanced lithography and etch techniques. Consequently, during the process sequence for patterning the gate electrode structure, the sensitive high-k dielectric material may be protected by the metal-containing material, possibly in combination with sophisticated sidewall spacer structures, thereby substantially avoiding any undue material modification during the further processing. After patterning the gate electrode structure, conventional and well-established process techniques for forming the drain and source regions having the desired complex dopant profile are typically performed. After any high temperature processes, the further processing may be continued, for instance, by forming a metal silicide, followed by the deposition of an interlayer dielectric material, such as silicon nitride, in combination with silicon dioxide and the like. In this manufacturing stage, a top surface of the gate electrode structures embedded in the interlayer dielectric material has to be exposed, which is accomplished by chemical mechanical polishing (CMP). The polysilicon material exposed during the CMP process is then removed and thereafter an appropriate masking regime may be applied in order to selectively fill in an appropriate metal for any type of transistors.
Although, in general, this approach may provide advantages in view of reducing process-related non-uniformities in the threshold voltages of the transistors since the high-k dielectric material, if provided in an early manufacturing stage, may be reliably encapsulated during the entire process sequence without requiring an adjustment of the work function and thus the threshold voltage at an early manufacturing stage, the complex process sequence for exposing and then removing the placeholder material and providing appropriate work function materials for the different types of transistors may also result in a significant degree of variability of the transistor characteristics, which may thus result in offsetting at least some of the advantages obtained by the common processing of the gate electrode structures until the basic transistor configuration is completed.
For example, an efficient removal of the polysilicon material may have a significant influence on the overall characteristics of the replacement gate, i.e., on the provision of appropriate work function metals for the N-channel transistor and P-channel transistor and the subsequent deposition of the actual metal-containing electrode material. For this purpose, typically, a dielectric cap layer in the form of a silicon nitride material may be maintained throughout the entire manufacturing process for forming the gate electrode structures and the basic transistor configuration, which may also act as a silicidation mask during the critical process step for forming metal silicide regions in the drain and source areas in order to suppress the formation of a metal silicide in the polysilicon material since any residues of the silicide material may not be efficiently removed. On the other hand, the cap layer has to be removed by the CMP process, which may result in process non-uniformities, as will be explained with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage in which a first semiconductor region 102A and a second semiconductor region 102B are formed in a semiconductor layer 102, which in turn is formed above a substrate 101. The substrate 101 typically represents a silicon-based carrier material above which is formed the semiconductor layer 102, for instance in the form of a silicon-based crystalline material. Moreover, in the manufacturing stage shown, a first gate electrode structure 110A is formed above the first semiconductor region 102A and a second gate electrode structure 110B is formed above the second semiconductor region 102B. Moreover, the regions 102A, 102B and the gate electrode structures 110A, 110B are covered by a spacer layer 103, such as a silicon nitride material. The gate electrode structures 110A, 110B may comprise a sophisticated layer stack, for instance comprising a sophisticated gate dielectric material 111 comprising any high-k dielectric material as specified above, in combination with a titanium nitride cap layer 114. Furthermore, a silicon material 112 is typically formed above the cap layer 114, followed by a dielectric cap layer 113 in the form of a silicon nitride material.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following well-established process techniques. First the semiconductor regions 102A, 102B may be formed by providing appropriate isolation structures in the semiconductor layer 102, for instance in the form of shallow trench isolations and the like, which, for convenience, are not shown in FIG. 1a. For this purpose, any appropriate process techniques may be applied. Thereafter, the complex gate material stack may be formed by oxidation and deposition techniques using any appropriate process recipes for obtaining the desired materials and the corresponding layer thickness values, such as for the gate dielectric material 111 and the cap layer 114. Thereafter, the silicon material 112 may be deposited on the basis of well-established low pressure chemical vapor deposition (CVD) techniques, followed by the deposition of the silicon nitride cap material 113. Furthermore, if required, any additional materials, such as hard mask materials and anti-reflective coating (ARC) materials, may be formed in accordance with requirements for the subsequent lithography and patterning strategies. Consequently, the gate electrode structures 110A, 110B are obtained with a desired critical length, i.e., in FIG. 1a, the horizontal extension of the material 112, which may be approximately 50 nm and less in sophisticated applications. Thereafter, the spacer layer 103 in the form of a silicon nitride material is deposited by using thermally activated CVD techniques or plasma-enhanced deposition recipes so as to obtain a desired layer thickness and material characteristics as required for the further processing. That is, the spacer layer 103 may be used for appropriately covering the sidewalls of the gate electrode structures 110A, 110B and in particular the sidewalls of the sensitive materials 111 and 114 during the further processing. Moreover, the spacer layer 103 may be used for providing sidewall spacers, which may additionally provide a corresponding lateral offset during the incorporation of dopant species for forming drain and source extension regions during the further processing of the device 100. In addition, corresponding sidewall spacer elements may be used as an etch and growth mask for incorporating a strain-inducing semiconductor material, for instance into the semiconductor region 102A, in order to create a desired strain component therein. It is well established that strain in the channel region of a field effect transistor may have a significant influence on the mobility of the charge carriers and may, therefore, result in a pronounced modification of drive current capability and thus performance of the transistor. For example, the generation of a compressive strain component in the channel region of P-channel transistors formed on the basis of a standard crystallographic configuration of a silicon layer may result in superior performance, which may be accomplished by incorporating a silicon/germanium alloy into the silicon material, which may result in a corresponding strained state, which may thus create a corresponding strain in the adjacent channel region. The incorporation of the silicon/germanium alloy is typically accomplished by forming cavities in the semiconductor region corresponding to the P-channel transistor, for instance the semiconductor region 102A, and subsequently refilling the cavities by using a selective epitaxial growth technique while substantially suppressing a material deposition on the semiconductor region 102B and the corresponding gate electrode structure 110B when representing an N-channel transistor.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a spacer element 103A is formed on sidewalls of the gate electrode structure 110A and may represent a remaining portion of the spacer layer 103, which is substantially completely preserved above the semiconductor region 102B and the gate electrode structure 110B. Moreover, the thickness of the silicon nitride cap layer 113 may be significantly reduced, as indicated by reference sign 113A. Additionally, a silicon/germanium alloy 104 is formed in the semiconductor region 102A with a lateral offset from the gate electrode structure 110A, i.e., from the material 112, that may be based on a thickness of the sidewall spacer 103A.
The semiconductor device 100 as illustrated in FIG. 1b may typically be formed on the basis of the following processes. After providing the spacer layer 103, the region 102B and the gate electrode structure 110B are masked, for instance by a resist material, and the exposed portion of the spacer layer 103 is etched so as to form the spacer elements 103A, which may be accomplished on the basis of any well-established anisotropic etch recipe. Thereafter, an appropriate etch chemistry is selected in order to etch into the semiconductor region 102A, thereby forming corresponding cavities, the offset of which may be defined on the basis of the spacer elements 103A and the characteristics of the corresponding etch recipe. It should be appreciated that, during the etch process, a certain amount of the silicon nitride cap layer 113 may be removed. Thereafter, the remaining resist material is removed and the device 100 is treated on the basis of appropriate cleaning recipes using wet chemical chemistries in order to prepare exposed surface portions for the subsequent selective epitaxial deposition of the silicon/germanium alloy. Thereafter, the silicon/germanium alloy 104 is deposited by applying well-established deposition recipes in order to refill and, if desired, overfill the previously formed cavities. During the selective epitaxial growth process, the silicon nitride cap layer 113A in combination with the spacer element 103A act as a mask, while the region 102B and the gate electrode structure 110B are still reliably covered by the spacer layer 103. As explained above, the spacer element 103A may also act as an offset spacer during a subsequent implantation process and consequently a corresponding spacer element is also to be formed on sidewalls of the gate electrode structure 110B. Consequently, the semiconductor region 102A and the gate electrode structure 110A are masked by resist material while the spacer layer 103 is exposed to an anisotropic etch ambient in order to form corresponding spacer elements, as is also described above for the spacer element 103A.
FIG. 1c schematically illustrates a cross-sectional view of the semiconductor device 100 in an advanced manufacturing stage. As illustrated, transistors 150A, 150B are formed in and above the active regions 102A, 102B in combination with the gate electrode structures 110A, 110B. The transistors 150A, 150B comprise drain and source regions 152 in combination with metal silicide regions 154. The drain and source regions 152 laterally enclose a channel region 153, which, in the transistor 150A, may have a certain compressive strain due to the presence of the silicon/germanium material 104. Furthermore, a spacer structure 151 may be formed on sidewalls of the gate electrode structures 110A, 110B, i.e., on the spacers 103A and spacer elements 103B that have been formed in accordance with the above-specified process sequence. It should be appreciated that, typically, the dielectric cap layer 113 of the gate electrode structure 110B may have a greater thickness compared to the dielectric cap layer 113A due to the difference in process history.
The transistors 150A, 150B may be formed on the basis of any appropriate process technique, for instance by incorporating appropriate dopant species in combination with providing the spacer structure 151, thereby obtaining the desired lateral and vertical dopant profile of the drain and source regions 152. After activating the dopant species and preparing exposed surface areas of the device 100 for the subsequent deposition of a refractory metal, such as nickel, platinum and the like, the metal silicide regions 154 are formed by well-established process techniques, wherein the dielectric cap layers 113A, 113 may act as a mask material in order to avoid the formation of a metal silicide in the polysilicon material 112. Next, an interlayer dielectric material 160 is formed, for instance, by depositing a first dielectric layer 161, such as a silicon nitride material and the like, which may act as an etch stop material for patterning a further dielectric material 162, possibly in combination with any additional dielectric materials still to be formed when forming contact openings in the interlayer dielectric material 160. In some cases, the material 161 may be provided in the form of a highly stressed material in order to create a desired type of strain in the channel region 153 of at least one of the transistors 150A, 150B. In sophisticated applications, the material 161 is provided with different types of internal stress above the transistors 150A, 150B in order to individually enhance performance of these devices. For this purpose, any appropriate manufacturing strategies are applied in order to deposit the desired material having the internal stress level and removing portions thereof from above one of the transistors 150A, 150B, for which the corresponding internal stress level may result in a deterioration of transistor performance.
FIG. 1d schematically illustrates the semiconductor device 100 during a polishing process 105, which may be applied so as to planarize the surface of the interlayer dielectric material 160 and to remove a portion thereof so as to finally expose the material 112. Generally, a polishing process, for instance in the form of a chemical mechanical polishing (CMP) process, may rely on the physical interaction of abrasive particles supplied by a slurry material and/or being present in a polishing pad, which may contact the material 160 on the basis of well-defined process parameters, such as relative speed between the material 160 and the polishing pad, the down force and the like. Furthermore, frequently, a chemical reaction may be concurrently initiated at the surface to be polished on the basis of appropriate chemical agents contained in the slurry material. Consequently, although CMP represents a very effective process for removing materials and concurrently providing a substantially planar surface topography, the removal of different materials, such as silicon dioxide, silicon nitride, possibly in differently stressed states, may represent a very complex process step, wherein a pronounced material removal between the gate electrode structures 110A, 110B is to be avoided as a metal-containing material will be deposited in the subsequent manufacturing stage. It turns out that, during the polishing process 105, in particular the removal of the cap layers 113A, 113 (FIG. 1c) may result in significant process non-uniformities, such as material residues of the cap layer which may still be present in a surface 112S of the polysilicon material 112. For example, typically, the cap layer 113 (FIG. 1c) may have an increased thickness, which may require a certain degree of over-polish time, which on the other hand may result in the generation and incorporation of any residues 160R in the material 112 of the gate electrode structure 110A, since the material 112 may be exposed earlier due to the reduced thickness of the dielectric cap layer 113A (FIG. 1c). Furthermore, the additional polish time may result in unwanted removal of material of the gate electrode structure 110A, thereby possibly unduly reducing the height thereof, which may also result in process and device irregularities upon finishing the semiconductor device 100. Furthermore, at any transition areas (not shown) of gate electrode structures of P-channel transistors and N-channel transistors, very sophisticated polish conditions occur, since here typically the layers 161 may have an increased thickness due to the previous patterning when differently stressed materials are to be used, while also the different thickness of the cap layers 113, 113S (FIG. 1c) may contribute to a very challenging process situation during the polishing process 105.
FIG. 1e schematically illustrates the semiconductor device 100 when exposed to an etch process 106 that is performed on the basis of an appropriate etch chemistry in order to remove the material 112 (FIG. 1d) selectively to the interlayer dielectric material 160 and the cap layer 114. For instance, very selective etch chemistries are available so as to efficiently remove polysilicon material substantially without unduly damaging the cap layer 114 and the underlying high-k dielectric material, while also substantially maintaining the dielectric materials. However, due to the presence of non-removed portions or any other polishing-related residues as described above with reference to FIG. 1d, the polysilicon material may not be completely removed so that corresponding residues 112R may still be present after the etch process 106. However, applying any pronounced over-etch times may not be a desirable option in view of integrity of the layers 114 and 111.
Consequently, during the further processing, i.e., during the deposition of metal-containing material layers for adjusting the work function of the gate electrode structures 110A, 110B and for providing a metal-containing electrode material, the polysilicon residues 112R significantly contribute to yield losses due to severe failures of the gate electrode structures or due to a pronounced variability in transistor characteristics.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.